CSCE 612: VLSI System Design - Computer Science & E

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CSCE 313 Embedded System DesignIntroductionInstructor Jason D Bakos Embedded SystemsCSCE 313 2.
Desktop vs Embedded CPU General purpose desktop and server CPUs have a more complex structure Execute up to 4 instructions per cycle Instructions executed out of order Big complex caches.
All code runs at the same speed since the processor finds parallelism at runtime Exception single core code will still only use one core SIMD instructionsoften require intrinsics Embedded CPUs Generally not reprogrammable except by vendor.
One or two instructions per cycle Instructions executed in order so instructions that depend on previous ones will hold up the line Small simple caches Performance is dependent on code efficiency.
Sometimes do not run an OS bare metal or limited OS support Tightly coupled with peripherials system on chip CSCE 313 3 Desktop vs Embedded CPU This class vs 240 and 274 .
Write code in C vs Java Write and debug code on a PC that runs on different Write code that communicates with hardware This class vs 274 Write code in C vs Python .
Write code that runs on bare metal Write code containing features to improve performance Code is more performance and graphics orientedCSCE 313 4 System on a Chip.
Most embedded processorscontain multiple CPUs andintegrated peripherals 2 CoprocessorsCSCE 313 5.
Field Programmable Gate Arrays Programmable logic device Contains Ability to implement soft logic programmable logic gates CLBs with programmable interconnect.
Hard cores RAMs multipliers IOs PCIe interface etc CSCE 313 6 Field Programmable Gate Arrays Originally developed for glue logic Now used as system on a programmable chip SoPC .
Customized softcore processor Memory cache subsystem I O interfaces Off chip memory interfacesCSCE 313 7.
FPGA Lookup Table Function generator CSCE 313 8 FPGA Fabric FPGA fabric .
CSCE 313 9 Field Programmable Gate Arrays On chip resources Logic Elements2 Register.
Onchip memories MultlipliersCSCE 313 10 Cyclone 2 Logic ElementCSCE 611 11.
Verilog Example Full adder module full adder input a b ci output s co assign s a b ci assign cout a b a ci b ci .
a b ci s cout Synthesize 0 0 1 1 0CSCE 611 12 Assume our target FPGA has LUT2s Can t map an 3 input function to one LUT2 .
information aboutCSCE 313 13 s a xor b xor c Equivalent to s a b c a b c a b c a b c .
Transform s a b c b c a b c b c s a b c b c a b c b c s a b c b c a b b b c b c c c s a b c b c a b c b c .
Set s0 b c b c s a s0 a s0 CSCE 313 14 Verilog Examplea b ci s a b ci s0 s.
a b ci s0 a b ci s0 s0 0 0 0 0 0 0 0 0X 0 0 0 0 X X 0 00 0 1 1 0 0 1 1 1X 0 1 1 0 X X 1 1.
0 1 0 1 0 1 0 1 1X 1 0 1 1 X X 0 10 1 1 0 0 1 1 0 0X 1 1 0 1 X X 1 01 0 0 1 1 0 0 0 1.
1 0 1 0 1 0 1 1 01 1 0 0 1 1 0 1 01 1 1 1 1 1 1 0 1CSCE 611 15 Place and Route.
CSCE 611 16 Terasic DE2 115 Altera Cyclone 4 FPGA with 115K gatesCSCE 313 17 System Design.
Processors communicate with the outside world using a simpletransactional model Processor says READ and provides an address Operations that depend on this data WAIT until data is returned WRITE .
Processor says WRITE and provides an address and data These operations correspond to the LOAD and STORE instructions In this case we assume that CPU is the master and devicesresponding to these operations are slavesCSCE 313 18.
Processor InterfaceInstruction interfaceInstructionIn InstructionAddressInstructionReadDataIn DataAddress.
Data interfaceCSCE 313 19 Programmed I O Loads and stores to specially mapped address ranges canbe used to .
Read a word from a status register Used to poll the state of a peripheral Write a word to a control register Used to send an instruction to a peripheralCSCE 611 20.
Sample Address MapCSCE 313 21 Altera Tools Quartus II Starting point for all designs create and open projects .
Contains simple editors for HDL design and constraint files Has a makefile like design flow manager for synthesis map place and route bitstream generation and programming Platform Designer Allows for drag and drop creations of platform designs.
processors busses peripherals Command line tools Compiler and run code on NIOS2 processorCSCE 313 22 Platform Designer.
Platform Designer allows you to design the portion of yourembedded system that is implemented on the FPGA Using this information the command line tools cangenerate a BSP that corresponds to your system The BSP includes the interface code for the peripherals that.
you add in SOPC Builder As such it must be regenerated each time you make a changein your system designCSCE 313 23 Setup Your Environment.
Do this once Open bashrc Add a line source usr local 3rdparty cad setup ... Log out log back in.
Launch Quartus CSCE 313 24CSCE 313 25 Creating a New Project File New New Quartus II Project .
Working directory acct username lights Project name lights Top level design entity lights Empty project Skip the Add Files page.
For device choose Family Cyclone IV E Package FBGA Pin count 780 Speed grade 7.
Device EP4CE115F29C7 Click Finish Go to Tools Platform DesignerCSCE 313 26 Platform Designer.
system configurationconfigurationCSCE 313 27 Adding Components Add a processor.
In the component library search for nios2 Double click Nios II Processor Select Nios II f then FINISH Add an interface to the SDRAM In the component library search for sdram .
Double click SDRAM Controller Intel FPGA IP Presets Bits 32 chip select 1 banks 4 row 13 column 10 then FINISH Add a clock manager In the component library search for clocks .
Double click System and SDRAM Clocks for DE series Boards Add another clock source In the component library search for clock source Double click clock source CSCE 313 28.
Connecting Clock and Reset Start with the clk 0 component connect clock output to ref clk on sys sdram pll 0 clk reset to ref reset on sys sdram pll 0 clk reset to reset on nios2 and sdram controller.
From sys sdram pll 0 sys clk to clk on nios2 gen2 0 reset source to reset to nios2 gen2 0 sdram clock to clk on new sdram controller From nios2 gen2 0 data master and instruction master to s1 on sdram.
From clk 1 clk in to sdram clk on sys sdram pll 0 Double click the Export column for clk Double click nios2 Under Vectors .
Reset and Exception vector memory sdram controller System Assign Base Addresses File Save As nios system CSCE 313 29 Platform Design.
CSCE 313 30 Platform Design Click Generate HDL Accept default settings Go back to Quartus.
Assignments Import Assignments usr local 3rdparty csce611 CP... DE2 115 pin assignments qsf Assignments Settings Files Add nios system qsys .
File New Synopsys Design Constraint File Contents create clock name CLOCK 50 period 20 get ports CLOCK 50 derive pll clocks create base clocks Save as SDC1 sdc.
File New Verilog HDL File Contents CSCE 313 31 Top Level DesignFPGA lights .
nios system NiosII CSCE 313 32 lights vmodule lights input CLOCK 50 input 3 0 KEY .
output 12 0 DRAM ADDR output 1 0 DRAM BA output DRAM CAS N output DRAM CKE output DRAM CS N .
inout 31 0 DRAM DQ output 3 0 DRAM DQM output DRAM RAS N output DRAM WE N output DRAM CLK .
nios system u0 clk clk CLOCK 50 clk clk reset reset n KEY 0 reset reset n new sdram controller 0 wire a... DRAM ADDR new sdram controller 0 wire ad... new sdram controller 0 wire b... DRAM BA ba.
new sdram controller 0 wire c... DRAM CAS N cas n new sdram controller 0 wire c... DRAM CKE cke new sdram controller 0 wire c... DRAM CS N cs n new sdram controller 0 wire d... DRAM DQ dq new sdram controller 0 wire d... DRAM DQM dqm.
new sdram controller 0 wire r... DRAM RAS N ras n new sdram controller 0 wire w... DRAM WE N we n sdram clk clk DRAM CLK CSCE 313 33 Hardware.
Re compile the design Program the FPGA Double click on Program DeviceCSCE 313 34 Hardware.
Click StartCSCE 313 35 Building and Running Software Go back to Quartus and compile your design Open terminal.
cd lights mkdir software cd softwarenios2 swexample create name lights sopc file nios system sopcinf... type hello world cpu name nios2 gen2 0 app dir lights bsp dir lights bsp.
cd lights create this appCSCE 313 36 hello world c Open hello world c.
include stdio h int main double new val 3 0 double val 0 double start 2 0 .
double temp int i 0 toggle 0 while val new val val new val temp start start 1 0 start 2 0 .
if toggle new val 4 0 temp new val 4 0 temp toggle toggle start start 2 0 .
printf value is 0 8f n val CSCE 313 37 Debugging nios2 gdb server tcpport 8888 tcppersist nios2 elf gdb lights elf.
target remote localhost 8888 b hello world c 39 p val 0 p val 3 p val 3 1667 .
p val 3 1333 p val 3 1416 p i 131072 CSCE 313 38 Common GDB Commands.
p print expression bt backtrace f frame c continue s step over .
n step into fin step out b breakpoint del delete breakpoint CSCE 313 39.
Adding Components Add a JTAG UART for the console use sys clk and global reset connect control slave to CPU Search uart add JTAG UART Intel FPGA IP Accept default settings connect as above.
Also connect irq to CPU Add parallel I O for the LEDs Search pio add PIO Parallel I O Intel FPGA IP Width 26 output ports only FINISH rename it as leds then put it on the Connect as above.
Double click export column and rename to leds Add parallel I O for the keys buttons Same as above but 3 bits input only Under Input Options turn on Synchronously capture then FINISH Rename as keys and put it on the sys clk.
CSCE 313 40 Adding ComponentsCSCE 313 41 lights vmodule lights input CLOCK 50 .
input 3 0 KEY output 12 0 DRAM ADDR output 1 0 DRAM BA output DRAM CAS N output DRAM CKE .
output DRAM CS N inout 31 0 DRAM DQ output 3 0 DRAM DQM output DRAM RAS N output DRAM WE N .
output DRAM CLK output 17 0 LEDR output 7 0 LEDGnios system u0 clk clk CLOCK 50 clk clk.
reset reset n KEY 0 reset reset n new sdram controller 0 wire a... DRAM ADDR new sdram controller 0 wire ad... new sdram controller 0 wire b... DRAM BA ba new sdram controller 0 wire c... DRAM CAS N cas n new sdram controller 0 wire c... DRAM CKE cke.
new sdram controller 0 wire c... DRAM CS N cs n new sdram controller 0 wire d... DRAM DQ dq new sdram controller 0 wire d... DRAM DQM dqm new sdram controller 0 wire r... DRAM RAS N ras n new sdram controller 0 wire w... DRAM WE N we n.
sdram clk clk DRAM CLK keys export KEY 3 1 keys export leds export LEDR LEDG leds exportCSCE 313 42 Note if you get the error .
XXX XXX overlaps XXX XXX Select System Assign Base Addresses Stop GDB pkill 9 gdb Download new SOF .
nios2 configure sof output files lights sof Update bsp cd lights bsp nios2 bsp generate files settings settings bsp bsp dir .
Altera Tools. Quartus II. Starting point for all designs (create and open . projects) Contains simple editors for HDL design and constraint files. Has a makefile-like design flow manager for synthesis, map, place and route, bitstream generation, and programming

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