CSCI 612: VLSI System Design

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CSCE 613 Fundamentals of VLSI Chip DesignInstructor Jason D Bakos MOSFET Theoryp type body majority carriers accumulation mode.
Vt depends ondoping and toxchannel is no longerat the same voltageas body channel.
becomes decoupledfrom body Fund of VLSI Chip Design 2 Regions of OperationGate to channel .
Vds Vgs VgdVgs near sourceVgd near drainSwitching delay isdetermined by .
time required tocharge discharge gate time for current totravel across channelFund of VLSI Chip Design 3.
Ideal I V CharacteristicsQchannel Linear region Q CV charge Qchannel C g Vgc Vt carrier time Vsd V Vgc Vgs Qchannel C g Vgs sd Vt 2 2 .
WL ox 3 9 0 C g ox Cox ox C g CoxWLtox 0 8 85 10 14 F cm toxQchannel CoxWL Vgs sd Vt v E carrier velocity is mobility .
V QchannelV electricv ds I ds E ds field carrier timeW V .
I ds Cox Vgs Vt ds VdsL L 2 carrier time v V I ds Vgs Vt ds Vds.
L2 2 carrier time W V Vds I ds k Vgs Vt ds VdsL 2 Fund of VLSI Chip Design 4.
Ideal I V CharacteristicsSaturation region WVds Vgs Vt Coxinto equation L nmos 0 Vgs Vt cutoff.
V I ds Vgs Vt ds Vds Vds Vdsat linear 2 V gs V 2t Vds Vdsat.
saturationHoles have less mobilitythan electrons so pmos s 2 3 pmosprovide less current and pare slower than nmos s of.
the same sizeWhich parameters do wechange to make MOSFETsFund of VLSI Chip Design 5 Fabrication.
Switching speed depends on Cg Cs and Cd Shrink minimum feature size Given fixed W L is reduced therefore less gate area However tox is also reduced Cgper stays constant.
However smaller channel length decreases carrier time Yields more current for per unit of W Therefore W may also be reduced for given current Cg Cs and Cd are reduced Transistor switches faster.
Fund of VLSI Chip Design 6 Nonideal I V Effects Velocity saturation and mobility degradation Lower Ids than expected At high lateral field strength V ds L carrier velocity stops increasing linearly with field.
At high vertical field strength V gs tox the carriers scatter more often Channel length modulation Saturation current increases with higher V ds Subthreshold conduction Current drops exponentially when V gs drops below Vt not zero .
Body effect Vt affected by source voltage relative to body voltage Junction leakage S D leaks current into substrate well Tunneling.
Gate current due to thin gate oxides Temperature dependence Mobility and threshold voltage decrease with rising temperatureFund of VLSI Chip Design 7 C V Characteristics.
Capacitors are bad Slow down circuit need to use more power creates crosstalk Gate is a good capacitor Gate is one plate channel is the other Needed for operation attracts charge to invert channel.
Source drain are also capacitors to body p n junction Parasitic capacitance Diffusion capacitance Depends on diffusion area perimeter depth doping levels and voltage.
Make as small as possible also reduces resistance Fund of VLSI Chip Design 8 Gate Capacitance Gate s capacitance Relative to source terminal.
Cgs COXWL Assuming minimum length Cgs Cper W Cper COXL OX tOX L Fab processes reduce length and oxide thickness.
simultaneously Keeps Cper relatively constant 1 5 2 fF um of widthFund of VLSI Chip Design 9 Gate Capacitance.
Five components Intrinsic Cgb Cgs CgdCgs overlap Cgd overlap C0 WLCox.
Parameter Cutoff Linear SaturationCgb C0 0 0 Cgsol Cgdol 0 2 Cgs 0 C0 2 2 3 C0 0 4 fF um ofCgd 0 C0 2 0Sum C0 C0 2 3 C0.
Fund of VLSI Chip Design 10 Parasitic Capacitance Source and drain capacitance From reverse biased PN junction diffusion to Csb Cdb.
Depends of area and perimeter of diffusion depth doping level voltage Diffusion has high capacitance and resistance Made small as possible in layout Approximately same as gate capacitance 1 5 .
2 fF um of gate width Isolated shared and mergeddiffusion regions for transistors inFund of VLSI Chip Design 11 Switch Level RC Delay Models.
Delay can beestimated asFET passing weakvalue has twicethe resistance.
Fund of VLSI Chip Design 12Cgs=CpermW Cperm = COXL = (eOX/tOX)L Fab processes reduce length and oxide thickness simultaneously Keeps Cperm relatively constant 1.5 – 2 fF / um of width Gate Capacitance Parasitic Capacitance Source and drain capacitance From reverse-biased PN junction (diffusion to body) Csb, Cdb Depends of area and perimeter of diffusion, depth, doping ...

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