Indium Phosphide Bipolar Integrated Circuits: 40 GHz and ...

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InGaAs InP DHBT s with 370 GHz f and fmaxusing a Graded Carbon doped BaseM Dahlstr m Z Griffith M Urteaga M J W RodwellUniversity of California Santa Barbara CA USAX M Fang D Lubyshev Y Wu J M Fastenau and W K Liu.
IQE Inc Betlehem PA USAgriffith ece ucsb edu mattias ece ucsb edu 805 893 8044 805 893 5705 fax Motivation for InP HBTsParameter InP InGaAs Si SiGe benefit simplified collector electron velocity 3E7 cm s 1E7 cm s lower c higher J.
base electron diffusivity 40 cm2 s 2 4 cm2 s lower bbase sheet resistivity 500 Ohm 5000 Ohm lower Rbbcomparable breakdown fieldsConsequences if comparable scaling parasitic reduction 3 1 higher bandwidth at a given scaling generation.
3 1 higher breakdown at a given bandwidthProblem for InP SiGe has much better scaling parasitic reductionPresent efforts in InP research communityDevelopment of low parasitic highly scaled high yield fabrication processesWhy mesa DHBT .
Continue to advance the epitaxial material for improved speed High speed HBT some standard figures of meritSmall signal current gain cut off frequency from H21 b c C je Cbc Rex Rc Cbc2 f qI c.
Maximum power gain from U 8 RbbCcb iCollector capacitance charging time when switching V How do we make HBT s faster .
Required transistor design changes required to double transistor bandwidthkey device parameter required changecollector depletion layer thickness decrease 2 1base thickness decrease 0 707 1emitter junction width decrease 4 1.
collector junction width decrease 4 1emitter resistance per unit emitter area decrease 4 1current density increase 4 1base contact resistivity decrease 4 1 if contacts lie above collector junction .
base contact resistivity unchanged if contacts do not lie above collector junction C s s C I s all reduced 2 1 easily derived from geometry resistivity velocity relationships How do we improve gate delay for digital IC s .
Gate Delay Determined by Depletion capacitance chargingthrough the logic swing in in VLOGIC Ccb Cbe depletion .
IC clock clock clock clockDepletion capacitance chargingDelay not well correlated with f through the base resistanceRbb Ccb Cbe depletion .
VLOGIC I C Ccb Cbe depl is 60 80 of total Supplying base collectorstored chargeHigh I C Ccb is a key HBT design objective through the base resistance.
Ccb VLOGIC VLOGIC Acollector TC IC IC 2VCE min Rbb b c Aemitter 2veffective VLOGIC Rex must be very low for low Vlogic at high J e.
The logic swing must be at least kT InP logic barely faster than SiGe VLOGIC 6 Rex I c q need to design for clock speed not f f max Scaling Laws Collector Current Density C cb charging time.
base Collector Field Collapse Kirk Effect Vcb J vsat qN d Tc2 2 Collector Depletion Layer Collapsebase Vcb min qN d Tc2 2 J max 2 vsat Vcb Vcb min 2 Tc2.
collector Note that Vbe hence Vcb Vce VLOGIC Acollector TC Ccb VLOGIC I C Acollector Tc VLOGIC IC VCE VCE min Aemitter 2vsat Collector capacitance charging time is reduced.
by thinning the collector while increasing current Challenges with ScalingCollector base scalingMesa HBT collector under base Ohmics Base Ohmics must be one transfer length sets minimum size for collector.
Solution reduce base contact resistivity narrower base contacts allowedUnavailable solution decouple base collector dimensionsCompromise physically undercut the collector semiconductorEmitter Ohmic Resistivity must improve in proportion to square of speed improvements.
Current Density self heating current induced dopant migration dark line defect formationLoss of breakdownavalanche Vbr never less than collector bandgap 1 12 V for Si 1 4 V for InP sufficient for logic insufficient for power.
submicron InP processes have progressively decreasing yield Fast DHBTs high current density high temperature Prof Ian HarrisonLow K Max Trise inof InGaAs CollectorTemperature Rise K .
SC ES C B E E Metal 0 2 0 0 2 0 4 0 6 0 8 1 1 2Distance from substrate m Thermal conductivity of InGaAs 5 W mK Thermal conductivity of InP 68 W mK Conclusion .
Minimize InGaAs thickness in subcollector Average Tj Base Emitter 26 20 C Measured Tj 26 C good agreement High f DHBT Layer Structure and Band DiagramInGaAs 3E19 Si 400 Vbe 0 75 V Vce 1 3 V.
InP 3E19 Si 800 InP 8E17 Si 100 InP 3E17 Si 300 InGaAs 8E19 5E19 C 300 Setback 3E16 Si 200 .
Grade 3E16 Si 240 InP 3E18 Si 30 Compared to previous UCSB mesa HBT results InP 3E16 Si 1030 Thinner InP collector decrease c.
InP 1 5E19 Si 500 InGaAs 2E19 Si 125 Collector doping increased increase JKirkInP 3E19 Si 3000 Thinner InGaAs in subcollector remove heat Thicker InP subcollector decrease Rc sheetSI InP substrate.
UCSB mesa HBT process flow UCSB mesa HBT process flow UCSB mesa HBT process flow UCSB mesa HBT process flow UCSB mesa HBT process flow.
InP HBT limits to yield non planar processEmitter contact liftoff failure Failureemitter emitter base modesbase short circuit base contactsub collector.
S I substratesub collectorEtch to base S I substratesub collectoremitter undercut base contact.
S I substrateLiftoff base metal contactsub collectorbase contact base contactS I substrate.
sub collectorS I substrateplanarization failure interconnect breaksEmitter planarization interconnectssub collector.
sub collector S I substrateS I substrateYield quickly degrades as emitters arescaled to submicron dimensions SEM of device before polymide passivation.
Profile of high frequency device Front view 0 6 um wide emitter by optical lithography 1 0 um thick Emitter contact width 0 6 um base mesa width 1 2 um emitters as small as 0 4 um wide fabricatedPhysical emitter width 0 5 um collector undercut 0 2 um self aligned base contact as small as 0 3 um on both.
sides of emitter Area collector Area emitter 1 0 0 5 2 Device results DC and Gummel plots for 150 nm collector10 A 0 6 x 7 m2 V 0V 0 18 I 0 4 mA I b.
J mA m2 b step 0 001I I mA 10 n 1 370 0 5 1 1 5 2 2 5 0 0 2 0 4 0 6 0 8 1.
V V V V Device dimensions DC gain 8 10 device area 4 2 m2 nc nb 1 04 1 55 emitter metal 0 7 x 8 mm Vbr CEO 5 V emitter junction 0 6 x 7 mm Jc 8 mA m2 Vce 2 5 V.
base mesa width 1 7 mJmax 12 mA m2 Vce 1 5 V Device results DC and rf f 370 GHz 10 A 0 6 x 7 mf 375 GHz.
8 I 0 4 mAJ mA m Gains dB 10 11 12 0 0 5 1 1 5 2 2 5Frequency Hz V V .
30 nm InGaAs base 8 1019 cm3 5 1019 cm3 base sheet 603 square150 nm InP collector base contacts 20 m20 6 x 7 m emitter emitter contacts 10 15 m20 5 m base contacts collector sheet 12 squarecollector contacts 9 m2.
S parameters and delay termsSmith chart Summary of delay termsDelay at this current point RelativeTau ec 430 fsRexCcb 13 fs 3 1 .
device simulation S22pdevice simulation S11pRexClay 9 fs 2 0 S21 20 tau f 314 fs 72 6 S12 x5 kT qI times Cje 71 fs 16 5 .
kT qI times Ccb 16 fs 3 6 kT qI times Clayout 10 fs 2 3 SUM 433 fs 100 0 ft corr 368 GHzS11 ft meas 370 GHz.
S22 Rex related 5 1 freq 5 000GHz to 40 00GHz freq 75 00GHz to 110 0GHz Device dimensions Extraction ex 10 m2 device area 4 2 m2.
vc 4 5 105 m s emitter metal 0 7 x 8 m emitter junction 0 6 x 7 m base mesa width 1 7 m Base metal resistance for very narrow contacts.
Resistance of e beam deposited metals higher than book values Metal resistivity increases when tbase metal 1000 AAu cm 0 500 1000 1500 2000 2500 3000 3500Gold thickness .
An important contributor to Rbb for the base contact Pd Ti Pd Au 25 170 170 630 s base metal 0 5 sq 3 8 added to Rbb for 0 3 m base contact width this will generate thermal instability if Rex is very low how low Base collector capacitance variation with J eV 0 3 V.
A fF um2 Ccb Ic 0 26 ps V0 2 4 6 8 10Je Ic Ae current density mA um Rf performance over time under bias.
freq 308 0GHz freq 308 0GHzdB baseline S 2 1 0 000 dB baseline S 2 1 0 000time 3 minutes f and fmax 308 GHz time 3 hours f and fmax 308 GHzDC bias conditions Vcb 0 35 V Vce 1 3 V J 8 5 mA m2 UCSB ONR Z Griffith.
UCSB static frequency divider designs w DRC 2003 model550 m Divider speed w 2 1 um 1 7 um 1 3 umbase mesa widthRex 15 Rbb 25.
113 127 143 m2 m2Rbb 20 115 129 145Rbb 15 117 132 148Rbb 10 120 135 152.
Rex 10 Rbb 25 119 133 149Rbb 20 121 135 151Rbb 15 123 138 154Rbb 10 125 141 158 Conclusions .
We have achieved record performance for f in a InP mesa DHBT 370GHz along withmaintaining simultaneously high fmax 375GHz Much of the gains attributed to the work on the process and the collector physical undercut thinning active material 2000A to 1500A.
doping higher to push Jkirk max higher thinning InGaAs subcollector contact 500A to 125A remove heatWhat are we concentrating on now in our mesa process Contact resistance need to drop Rex for simultaneous increase in ft and fmax Find way to increase base metal thickness high ft and without lowing fmax.
Alternative base grade scheme dual grade doping and alloyAcknowledgment This work is supported by the Office of Naval Research under contract N00014 01 1 0024 S parameter measurement test structureOn wafer LRL calibration .
LRL calibration using on wafer Open Zero length through line and delay line OSLT used to check U in DC 50 GHz band Probe pads separated by 460 m to reduce p p coupling RF environment not ideal need thinning air bridges vias for parasitic modesuppression.
SEM of patterned passivation w interconnectsPatterned polyimide passivation plasma etch Coplanar waveguide interconnectsCcb/Ic 0.26 ps / V time = 3 minutes, f and fmax 308 GHz time = 3 hours, f and fmax 308 GHz DC bias conditions: Vcb = 0.35 V, Vce 1.3 V J = 8.5 mA/ m2 158 141 125 Rbb = 10 154 138 123 Rbb = 15 151 135 121 Rbb = 20 149 133 119 Rbb = 25 Rex = 10 152 135 120 Rbb = 10 148 132 117 Rbb = 15 145 129 115 Rbb = 20 143 127 113 Rbb = 25 W×mm2 Rex = 15 W ...

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