Lecture 10 MOSFET

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CCE201 Solid State Electronic DevicesEEC223 Electronics 1 Lecture 08Field Effect Transistors 1 Prepared By.
Dr Eng Sherif HekalAssistant Professor CCE departmentLecture 01 10 16 2020 1 IntroductionIN THIS LECTURE WE WILL LEARN.
General overview on FET transistor and its types The physical structure of the MOS transistor andhow it works How the voltage between two terminals of thetransistor control the current that flows through.
the third terminal and the equations thatdescribe these current voltage characteristics How the transistor can be used to make an10 16 2020 2amplifier and how it can be used as a switch in.
digital circuits IntroductionQ What in simplest terms is the desiredoperation of a three terminal device A Employ voltage between.
two terminals to controlcurrent flowing in to the third 10 16 2020 3 note MOSFET is more widely used inimplementation of modern electronic.
Introduction Q What are two major types of MOSFET technologythree terminal semiconductordevices It allows placement of metal oxide semiconductor approximately 2 billion.
field effect transistor transistors on a single MOSFET IC bipolar junction transistor backbone of very BJT large scale Q Why are MOSFET s more integration VLSI .
widely used It is considered size smaller preferable to BJT ease of manufacture technology for many lesser power utilization applications .
10 16 2020 4 Differences between FETField Effect TransistorBJT Bipolar Junction FET Transistor BJT .
Unipolar Bipolar1 Current depends only on Current depends on bothone type of carriers electrons and holes2 Voltage controlled device Current controlled device3 Very high input impedance Low input impedance.
Simpler in fabrication andoccupies large space in4 occupies less space inintegrated formintegrated form.
Low voltage gain High voltage gainHigh current gain Low current gain6 Easily damaged Robust10 16 2020 5 Field Effect Transistor.
The name Field Effect Transistor arises from the fact that thecurrent flows between two terminals Drain D Source S is controlled by an electric field which is applied on the thirdterminal Gate G FET D MOSFET.
10 16 2020 6 Junction Field Effect Transistor J FET Physical Structure n channel It consists of bar of n type silicon with p type silicon diffused on both sides each.
p region is called gate In most cases the two gates are internally connectedand the device acts like a single gateSource S is the terminal throughwhich the majority carriers enter the.
Drain D is the terminal through whichthe majority carriers leave the channel 10 16 2020 7Channel the region of n type materialbetween the drain and source terminals .
Junction Field EffectTransistor J FET Biasing of N channel JFETThe drain terminal should be ve relative to the sourceThe gate terminal should be ve relative to the source 8.
10 16 2020 Junction Field Effect Transistor J FET Physical operation of the n channel JFET a For small the channel is uniform and the device functions as a resistancewhose value is controlled by more in negative larger depletion region .
narrower channel lower current b Increasing causes the channel to acquire a tapered shape and eventuallypinch off occurs so the current reaches the max value If 10 16 2020 the max value Junction Field Effect.
Transistor J FET Active Pinch off region.
Transfer Characteristics V I Characteristics 10 16 2020 10 Junction Field Effect.
Transistor J FET Pinch offGate control region if regionis the pinch off voltage 10 16 2020 11.
Equations in activedrain current Collector currentSource current Emitter currentis the maximum drain current for a JFET and is defined by10 16 2020 12.
the conditions and Difference between JFETD MOSFET E MOSFETDepletion type Enhancement typeThe key difference between JFET and MOSFET is that the.
gate terminal in MOSFET is insulated from the channel Because of this insulated gate the input impedance of a10 16 2020 13MOSFET is many times higher than that of a JFET 1 Device Structure and.
Figure 1 Physical structure of the enhancement type NMOS transistor a perspective view b cross section Note that typically L 0 03um to 1um W 0 1um to 100um and the thickness of the oxide layer tox is in the range of 1 to 10nm 10 16 2020 14 two n type doped.
regions drain source 1 Device Structure layer of SiO2 separatessource and drainand Operationmetal placed on top of.
SiO2 forms gateone p type doped regionFigure 1 Physical structure of the enhancement type NMOS transistor a perspective view b cross section Note that typically L 0 03um to 1um W 0 1um to 100um and the thickness of the oxide layer tox is in the range of 1 to 10nm 10 16 2020 15.
1 Device Structure and The name MOSFET is The device isderived from its physical composed of two pn structure junctions however.
However many MOSFET s they maintain reversedo not actually use any metal polysilicon is usedbiasing at all times instead Drain will always be at.
This has no effect on positive voltage withmodeling operation as respect to source described here We will not consider Another name for MOSFET.
is insulated gate FET orconduction of currentIGFET in this manner 10 16 2020 16 1 2 Operation with Zero.
Gate Voltage With zero voltageapplied to gate twoback to back diodesexist in series between.
drain and source They prevent currentconduction from drainto source when avoltage vDS is applied .
yielding very highresistance 1012ohms Physical structure of MOSFET10 16 2020 17 1 3 Creating a Channel forCurrent Flow.
Q What happens if 1 sourceand drain are grounded and 2 positive voltage is appliedto gate Refer to figure to step 1 vGS is applied to.
the gate terminal causinga positive build up ofpositive charge alongmetal electrode step 2 This build up .
causes free holes to berepelled from region of p type substrate under gate Figure 2 The enhancement type NMOS transistorwith a positive voltage10 16 2020applied to the.
gate An nchannel is induced at the top of the substratebeneath the gate Q What happens if 1 source and drain aregrounded and 2 positive voltage is applied to.
gate Refer to figure to right step 3 This migration results in theuncovering of negativebound charges .
originally neutralized bythe free holes step 4 The positivegate voltage also attractselectrons from the n .
source and drain regionsinto the channel Figure 2 The enhancement type NMOS transistorwith a positive voltage10 16 2020applied to the.
gate An nchannel is induced at the top of the substratebeneath the gate this induced channel isalso known as an.
inversion layerQ What happens if 1 source and drain aregrounded and 2 positive voltage is applied togate Refer to figure to right step 5 Once a.
sufficient number of these electronsaccumulate an n region is created connecting the source.
and drain regions step 6 This providespath for current flowbetween D and S Figure 2 The enhancement type NMOS transistor.
with a positive voltage10 16 2020applied to thegate An nchannel is induced at the top of the substratebeneath the gate.
1 3 Creating a Channel forCurrent Flow threshold voltage Vt is the effective overdriveminimum value of vGS requiredvoltage is the.
to form a conducting channelbetween drain and source difference between vGS typically between 0 3 andapplied 1 Vtv OV vGS Vt field effect when positive vGS.
is applied an electric fielddevelops between the gate oxide capacitance Cox electrode and induced n is oxthe capacitanceis permittivity ofE 11 F m of SiO2 3 45.
channel the conductivity of tox is thickness of SiO2 layerthe parallel plate this channel is affected by thestrength of field capacitor per unit oxgate 2.
area Eq F m 3 C2 in F m SiO2 layer acts as dielectric tox10 16 2020 21 1 3 Creating a Channel for.
Current Flow Q What is main requirement Q How can one express thefor n channel to form magnitude of electron charge A The voltage across the contained in the channel oxide layer must exceed.
Vt A See below W and L represent width and length of channel respectively For example when vDS 0 the voltage at every point Eq 3 Q C ox WL vOV in C.
along channel is zero the voltage across theoxide layer is uniform and Q What is effect of vOV on n equal to vGS channel A As vOV grows so does the.
depth of the10 16 2020n channel22 as wellas its conductivity 1 4 Applying a Small vDS Q For small values of vDS how does one calculate iDS aka .
iD A Equation 4 Q What is the origin of this equation A Current is defined in terms of charge perunit length of n channel as well as electrondrift velocity .
n represents mobility of electrons at surface of then channel in m2 Vs nvDS Eq 4 D ox.
eq5 7 i C W v OV in A L charge per unitlength of electron.
n channel drift velocityin C m in m2 Vs 10 16 2020 23 1 4 Applying a Small vDS Q What is observed from equation 4 A For small values of vDS the n channel acts like.
a variable resistance whose value is controlled Eq 5 iD nC ox eq5 7 vOV vDS in A L Eq 6 rDS in .
iD W nC ox vOV L 10 16 2020 24transconductance aspectparameter ratio.
1 4 Applying a Small vDS Q What three factors is rDS dependent on A process transconductance parameterfor NMOS mnCox which is determined bythe manufacturing process.
A aspect ratio W L which is dependenton size requirements allocations A overdrive voltage vOV which isapplied by the user10 16 2020 25.
kn is known as NMOS FETtransconductance parameterand is defined as mnCoxW Llow resistance high vOVhigh resistance low vOV.
10 16 2020 26Figure 4 The iD vDS characteristics of the MOSFET in Figure 5 3 whenthe voltage applied between drain and source VDS is kept small 1 5 Operation as vDS is Q What happens to iD when vDS increases beyond small.
values A The relationship between them ceases to be linear Q How can this non linearity be explained step 1 Assume that vGS is held constant at value greater than Vt step 2 Also assume that vDS is applied and appears as voltage.
drop across n channel step 3 as vDS is Increased the depletion layer between p type body and n type channel near the drain increases and so thecross section area of the channel near the drain decreases asshown in Fig 5 Hence as vDS is Increased the current slowly.
increased nonlinear relation and this region is called near pinch When vDS vov the channel near the drain completely pinched off10 16 2020 27and the current flows in the channel saturates reach to themaximum value This region is called pinch off Saturation or.
active saturation occursonce vDS vOV triode Cn ox v OV 2 v DS v DS.
if vDS vOV eq5 14 i Eq D in A7 saturation 1 nC ox W vO2 V otherwis10 16 2020 2 L.
Example 1 NMOS MOSFET Example 5 1 Problem Statement Consider an NMOSprocess technology for which Lmin 0 4mm tox 8nm n 450cm2 Vs Vt 0 7V Q a Find Cox and k n .
Q b For a MOSFET with W L 8mm 0 8mm calculatethe values of vOV vGS and vDSmin needed to operate thetransistor in the saturation region with dc current ID Q c For the device in b find the values of vOV and vGSrequired to cause the device to operate as a 1000ohm.
10 16 2020 29resistor for very small vDS Example 1 Sol10 16 2020 30 Example 1 Sol Cont .
It consists of bar of n-type silicon with p-type silicon diffused on both sides, each “p” region is called gate. In most cases, the two gates are internally connected and the device acts like a single gate. Source (S): is the terminal through which the majority carriers enter the channel. Drain (D):

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