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Workshop on Frontiers of Extreme ComputingSanta Cruz CAOctober 24 2005ITRS MOSFET Scaling Trends Challenges andKey Technology Innovations.Peter M Zeitzoff Introduction MOSFET scaling and its impact Material and process approaches and Non classical CMOS. ConclusionsSEMATECH the SEMATECH logo AMRC Advanced Materials Research Center ATDF the ATDF logo AdvancedTechnology Development Facility ISMI and International SEMATECH Manufacturing Initiative are servicemarks ofSEMATECH Inc All other servicemarks and trademarks are the property of their respective owners 08 10 20 2. Introduction IC Logic technology following Moore s Law by rapidly scalinginto deep submicron regime Increased speed and function density Lower power dissipation and cost per function. The scaling results in major MOSFET challenges including Simultaneously maintaining satisfactory Ion drive current and Ileak High gate leakage current for very thin gate dielectrics Control of short channel effects SCEs for very small transistors Power dissipation. Potential solutions approaches Material and process front end high k gate dielectric metal gateelectrodes strained Si Structural non classical CMOS device structures Many innovations needed in rapid succession.08 10 20 3 International Technology Roadmap forSemiconductors ITRS Industry wide effort to map IC technology generations forthe next 15 years. Over 800 experts from around the world From companies consortia and universities For each calendar year Projects scaling of technology characteristics and requirements basedon meeting key Moore s Law targets. Assesses key challenges and gaps Lists best known potential solutions Projections are based on modeling surveys literature experts technical judgment This talk is based on both the 2003 ITRS and on preliminary.data from 2005 ITRS not yet released 08 10 20 4 Key Overall Chip Parameters for High Performance Logic Datafrom 2003 ITRSYear of Production 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018.Technology Node hp90 hp65 hp45 hp32 hp22DRAM Pitch nm 100 90 80 70 65 57 50 45 35 32 25 22 18MPU PhysicalGate Length 45 37 32 28 25 22 20 18 14 13 10 9 7Vdd V 1 2 1 2 1 1 1 1 1 1 1 1 1 0 9 0 9 0 8 0 8 0 7.Chip FrequencyOn chip local2 976 4 171 5 204 6 783 9 285 10 972 12 369 15 079 20 065 22 980 33 403 39 683 53 207Maximum Powerperformance.149 158 167 180 189 200 210 218 240 251 270 288 300with heatsinkCost performance80 84 91 98 104 109 114 120 131 138 148 158 168Functions per chip.at production153 193 243 307 386 487 614 773 1 227 1 546 2 454 3 092 4 908 million transistors Mtransistors Technology generations defined by DRAM half pitch. Gate length Lg 0 5 X DRAM half pitch Rapid scaling of Lg is driven by need to improve transistor speed Clock frequency functions per chip density scale rapidly but allowablepower dissipation rises slowly with scaling limited by ability to remove08 10 20 5. Introduction MOSFET scaling and its impact Material and process approachesand solutions Non classical CMOS. Conclusions08 10 20 6 MOSFET Scaling Approach 2005 ITRS MASTAR computer modeling software is used detailed analytical MOSFET models with key.MOSFET physics included Initial choice of scaled MOSFET parameters is made Using MASTAR MOSFET parameters are iterativelyvaried to meet ITRS targets for either Scaling of transistor speed OR. Specific low levels of leakage current08 10 20 7 ITRS Drivers for Different Applications High performance chips MPU for example Driver maximize chip speed maximize transistor.performance metric transistor intrinsic delay or equivalently 1 Goal of ITRS scaling 1 increases at 17 peryear historical rate Must maximize Ion. Consequently Ileak is relatively high Low power chips mobile applications Driver minimize chip power to conserve batterypower minimize Ileak Goal of ITRS scaling low levels of I leak. Consequently 1 is considerably less than forhigh performance logic This talk focuses on high performance logic which largely drives the technology 1 and Isd leak scaling for High Performance and Low .Power Logic Data from 2003 ITRS Isd leak High Perf1 High Perf1 Low PowerIsd leak Low Power.17 yr ave increase08 10 20 9 Frequency scaling Transistor Intrinsic Speed andChip Clock Frequency for High Performance Logic Data from 2003 ITRS .Intrinsic 1 Chip clock ITRS projectionChip Clock assumption is thatonly improvement here is fromtransistor speed increase.Conclusion transistor speedimprovement is a critical enabler ofchip clock frequency improvement08 10 20 10 Potential Problem with Chip Power Dissipation Scaling .High Performance Logic Data from 2003 ITRSRelative Chip Power DissipationProjected cooling capability Static2003 2005 2007 2009 2011 2013 2015 2017Calendar Year.Unrealistic assumption to make a point about Pstatic all transistors are high performance low Vt type08 10 20 11 Potential Solutions for Power DissipationProblems High Performance Logic. Increasingly common approach multiple transistortypes on a chip multi Vt multi Tox etc Only utilize high performance high leakage transistors incritical paths lower leakage transistors everywhere else Improves flexibility for SOC. Circuit and architectural techniques pass gates power down circuit blocks etc Improved heat removal electro thermal modelingand design Electrical or dynamically adjustable Vt devices. future possibility 08 10 20 12 Introduction MOSFET scaling and its impact Material and process approaches.and solutions Non classical CMOS Conclusions08 10 20 13 Difficult Transistor Scaling Issues. Assumption highly scaled MOSFETs with thetargeted characteristics can be successfullydesigned and fabricated However with scaling meeting transistorrequirements will require significant technology.innovations Issue High gate leakage static power dissipation Direct tunneling increases rapidly as Tox is Potential solution high k gate dielectric Issue Polysilicon depletion in gate electrode .increased effective Tox reduced Ion Issue Need for enhanced channel mobility08 10 20 14 For Low Power Logic Gate Leakage Current Density Limit VersusSimulated Gate Leakage due to Direct Tunneling Data from 2003 ITRS .1 00E 03 24Jg simulated 211 00E 02 EOT 201 00E 01 16Jg A cm2 .1 00E 00 121 00E 01 Jg limit 81 00E 02 Beyond this point of cross over 4oxy nitride is incapable of 3meeting the limit Jg limit on gate 2.1 00E 03 leakage current density 02003 2005 2007 2009 2011 2013 2015 2017Calendar Year2006 EOT 1 9 nm Jg max 0 007 A cm 208 10 20 15. High K Gate Dielectric to Reduce Direct TunnelingTox SiO2 High k MaterialElectrode ElectrodeSi substrateSi substrate. Equivalent Oxide Thickness EOT Tox TK 3 9 K where 3 9 is relativedielectric constant of SiO2 and K is relative dielectric constant of high K C Cox ox Tox To first order MOSFET characteristics with high k are same as for SiO2 Because TK Tox direct tunneling leakage much reduced with high K. If energy barrier is high enough Current leading candidate materials HfO2 Keff 15 30 HfSiOx Keff 12 16 Materials process integration issues to solve08 10 20 16 Difficult Transistor Scaling Issues. With scaling meeting transistorrequirements requires significanttechnology innovations Issue High gate leakage static powerdissipation. Potential solution high k gate dielectric Issue polysilicon depletion in gate electrode increased effective Tox reduced Ion Potential solution metal gate electrodes Issue Need for enhanced channel mobility.08 10 20 17 Polysilicon Depletion and SubstrateQuantum Effects Tox electric Tox Kox Ksi Wd Poly Kox 3 9.Depletion Layer Ksi 11 9Polysilicon Wd PolyGate Tox electric Tox 0 33 Wd Poly Wd Poly 1 poly doping 0 5 increase poly doping to.Gate Oxide reduce Wd Poly with scaling But max poly doping islimited can t reduce Wd PolySubstrate Poly depletion become morecritical with Tox scaling. Eventually poly will reachInversion Layer its limit of effectiveness08 10 20 18 Metal Gate Electrodes Metal gate electrodes are a potential solution.when poly runs out of steam probablyimplemented in 2008 or beyond No depletion very low resistance gate no boronpenetration compatibility with high k Issues. Different work functions needed for PMOS and NMOS 2different metals may be needed Process complexity process integration problems cost Etching of metal electrodes New materials major challenge.08 10 20 19 Difficult Transistor Scaling Issues With scaling meeting transistor requirementsrequires significant technology innovations Issue High gate leakage static power dissipation. Potential solution high k gate dielectric Issue Poly depletion in gate electrode increasedeffective Tox reduced Ion Potential solution metal gate electrodes Issue Need for enhanced channel mobility. Potential solution enhanced mobility via strainengineering08 10 20 20 Uniaxial Process Induced Stress forEnhanced Mobility.PMOS uniaxial compressiveNMOS uniaxial tensile stress stress from sel SiGe in S Dfrom stressed SiN filmFrom K Mistry et al Delaying Forever Uniaxial StrainedSilicon Transistors in a 90nm CMOS Technology 2004 VLSI.Technology Symposium pp 50 51 08 10 20 21 Results from Uniaxial Process InducedNMOS Id sat PMOS Id linFrom K Mistry et al Delaying Forever Uniaxial Strained Silicon Transistors in.a 90nm CMOS Technology 2004 VLSI Technology Symposium pp 50 51 08 10 20 22 Introduction Scaling and its impact Material and process approaches.and solutions Non classical CMOS Conclusions08 10 20 23 Limits of Scaling Planar Bulk MOSFETs. 65 nm tech generation 2007 Lg 25nm andbeyond increased difficulty in meeting all devicerequirements with classical planar bulk CMOS even with high k metal electrodes strained Si Control of SCE. Impact of quantum effects and statistical variation Impact of high substrate doping Control of series S D resistance Rseries s d Others Alternative device structures non classical.CMOS may be utilized Ultra thin body fully depleted single gate SOIand multiple gate transistors08 10 20 24 Transistor Structures Planar Bulk Fully Depleted SOI.Planar Bulk Fully DepletedDepletion RegionSubstrate Substrate Wafer cost availability Lower junction cap Light doping possible. SCE scaling difficult Vt can be set by WF of High doping effects and Metal Gate Electrode SCE scaling difficultStatistical variation Sensitivity to Si Parasitic junction thickness very thin .capacitance Wafer cost availability1 P M Zeitzoff J A Hutchby and H R Huff MOSFET and Front End Process Integration ScalingTrends Challenges and Potential Solutions Through The End of The Roadmap International Journal ofHigh Speed Electronics and Systems 12 267 293 2002 2 Mark Bohr ECS Meeting PV 2001 2 Spring 2001 .08 10 20 25 Field Lines for Single Gate SOI MOSFETsE Field linesTo reduce SCE s aggressively reduce.Si layer thicknessRegular SOI MOSFET Double gate MOSFETSingle Gate SOICourtesy Prof J P Colinge UC Davis08 10 20 26. Double Gate Transistor StructureREFERENCES1 P M Zeitzoff J A Hutchby and H R Huff MOSFET and Front EndProcess Integration Scaling Trends Challenges and PotentialSolutions Through The End of The Roadmap International Journal of.High Speed Electronics and Systems 12 267 293 2002 2 Mark Bohr ECS Meeting PV 2001 2 Spring 2001 Double Gate SOI Enhanced scalability Lower junction capacitance. Light doping possibleBottom Vt can be set by WF ofBOX metal gate electrodethin FD 2x drive current 2x gate capacitance. High Rseries s d raised S D Complex processSummary more advanced optimaldevice structure but difficult tofabricate particularly in this SOI.configuration08 10 20 27 Field Lines for Single and Double Gate MOSFETsTo reduce SCE s .* The LSTP EOT scaling scenario has been slightly changed to make it a more linear function of time (1A/year). * For the HP, LOP, and LSTP scaling scenarios, some form of dual-gate device has been assumed to be available by 2012 (each of the Param-Dual-Gate parameters has been set to 0.5).